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Intellectt Inc · Raleigh, North Carolina
Job ID:
536707
Client:
Eaton
Raleigh, NC
Verilog & VHDL RTL Design
FPGA Design & Debug
CDC & Interface Protocols Understanding
Strong Verilog HDL and RTL design expertise.
Good knowledge of CDC, reset design, pipelining, FIFO/memory, and synchronization.
Strong understanding of STA, timing constraints, timing closure, and clock architecture.
Industries: Semiconductor, FPGA Design, Embedded Systems, Electronics, Hardware Engineering.
Target Companies: FPGA development, semiconductor, and electronics hardware companies.
Locations: Raleigh, NC, and candidates open to working onsite in Raleigh.
Priority 1
Strong Verilog HDL and VHDL RTL design.
FPGA design, debugging, and hardware bring-up.
CDC (Clock Domain Crossing) and synchronization.
STA, timing constraints, and timing closure.
Priority 2
Knowledge of Questa/ModelSim simulation tools.
Hands-on FPGA board-level debugging.
FPGA implementation and debugging projects.
FPGA tools: Vivado, Quartus, or Libero.
Candidates with significantly less or more experience than the required 5–7 years.
Education &
Intellectt Inc. is an Equal Opportunity Employer. Employment decisions are made without regard to race, color, religion, sex, pregnancy, sexual orientation, gender identity, national origin, age, disability, genetic information, veteran status, or any other characteristic protected by applicable federal, state, or local law.
Details
| Company | Intellectt Inc |
| Location | Raleigh, North Carolina |
| Type | FULL TIME |
| Niche | Full-time |